Tutorial 10 - Sequential Logic Systems

What is a sequential circuit?

We have looked at combinational logic systems in which the output was determined by the combinations of one or more inputs.  The output state at any time is dependent on the state of the inputs.  In a sequential circuit, the output is dependent on:

• The current input to the circuit;

• The previous inputs to the circuit.

In effect the circuit has a memory.

Sequential circuits are the basic building blocks of:

• Counters;

• Shift registers;

• Memories.

In synchronous sequential circuits, changes in output do not occur immediately there is a change in input, but the next time there is a clock pulse.  In asynchronous circuits the next stage is triggered by the completion of the previous stage without reference to a clock pulse.

Clock pulses are square wave oscillations that are produced by a pulse generator that can be based on two kinds of circuit:

• Astable generators produce trains of square waves;

• Monostables produce single pulses.

Circuits are triggered in one of two ways:

• Level triggering in which the changes occur when the level of the pulse is either at 0 or 1.

• Edge triggering in which the change occurs as the clock pulse rises from 0 to 1(rising or positive edge) or from 1 to 0 (falling or negative edge).

The diagram shows the idea. Level sensitive devices are often referred to as latches, while edge triggered devices are called flip-flops.  Pulses can be provided manually with switches, but they can provide spurious pulses due to bounce.  They can be de-bounced using a Schmitt trigger, which also can be used to clean up noisy signals.

 What is the difference between pulses produced by a monostable and an astable? What is the behaviour you would expect from a synchronous falling edge triggered flip-flop?

Here some important definitions to learn.

 Term Definition Combinational circuit The output is determined by the combinations of one or more inputs. Sequential circuit Output is dependent on: The current input to the circuit; The previous inputs to the circuit. Synchronous Changes in output do not occur immediately there is a change in input, but the next time there is a clock pulse Asynchronous The next stage is triggered by the completion of the previous stage without reference to a clock pulse Triggering Level triggering in which the changes occur when the level of the pulse is either at 0 or 1. Edge triggering in which the change occurs as the clock pulse rises from 0 to 1(rising or positive edge) or from 1 to 0 (falling or negative edge). Flip-Flop Edge triggered devices are called flip-flops. Latch Level sensitive devices are often referred to as latches

Bistable Latches

Bistables have two stable states; one output remains high while the other remains low.  These are complementary states.  The situation remains until an external input signal such as a clock pulse switches the complimentary states over.

We can use two NAND gates to produce an S-bar - R-bar latch.  The circuit diagram is shown below. There are two inputs to the latch, the set, S-bar, and the reset, R-bar.  There are two output states, Q and Q-bar which are complementary to each other.  This means that when Q = 0, Q-bar = 1, and vice versa.  The common symbol for the latch is not the circuit diagram above, but either of the alternatives shown. This bistable is the industry standard, made from NAND gates.  We say that its inputs are active-low which means that the state changes when the inputs go low.

We can draw up a truth table, often called a transition table for the circuit.  We can also show what is happening in a timing diagram, which is three voltage-time graphs stacked one on top of the other.

 S-bar R-bar Q Q-bar Notes 0 1 1 0 S-bar = 0 sets Q = 1 (SET) 1 1 1 0 Outputs remain in previous states 1 0 0 1 R-bar = 0 sets Q-bar = 1 and Q = 0 (RESET) 1 1 0 1 Outputs remain in previous states 0 0 0 0 Indeterminate state (not allowed) When S-bar falls from 1 to 0, there is no effect until the R-bar falls from 1 to 0.  Then the output Q changes from 1 to 0.  Then R-bar goes to 1, but there is no change in Q until S-bar goes to 1.

This  latch is a circuit that can be used to de-bounce a switch, cleaning its action to get rid of unwanted pulses.  The layout is shown in the diagram: Let us analyse the circuit as the switch is moved from B to A.

 Switch Position S-bar R-bar Q 1 0 0 1 1 0 0 1 1 1 1 1 0 1 1

Notice how the output does not change as the switch bounces.

There is one disadvantage about the S – R bistable circuit, and that is what happens when both the inputs are 0.  This is an indeterminate state and the output is not predictable.  We cannot say if the bistable will return to the SET or the RESET state.  We can avoid this by ensuring that the inputs are changed alternately.

 What is the problem with there being an indeterminate state?

The D-type Flop-Flip

Latches can be used to act as memories, but have a major problem.  They can be what is called transparent.  If one of the inputs is high, and the other is connected to a clock impulse, the output will change as the clock pulses pass through.  Let us think about this more using the S – R latch (made from NOR gates).  Data is put in through the S input while the R input is connected to a square wave pulse generator as below. This latch is active high, which means that it changes state when S or R goes high.  We start off with R low and S changing from low to high and back again.  The output Q is low.  Then we change R to high and this should give us a high at the output Q.  We get that initially, but when the input S goes low, the output goes low.  When it goes high, the output goes high as well.  This situation lasts as long as R stays high.  So we get the clock pulse passing through the latch, which is why we call it transparent.  This can be a nuisance in computers and other systems where data changes rapidly.

We can overcome this problem by using edge-triggering.  Bistables that use edge triggering are called flip-flops.  Flip-flops do not have this problem with being transparent.  The D-type flip-flop is the basic design unit for sequential circuits, which are circuits whose outputs change with time.  The symbol with the D-type flop-flip is shown. We should note the following about the flip-flop:

• The outputs are complimentary.  When Q is 1, Q-bar is 0 and vice versa.

• Terminal S and R are there to set and reset the flip-flop.  Signals at these inputs take priority over the other two inputs

• The data input takes in the data, while the clock input takes in the clock pulses.  The triangle indicates edge triggering.  An upward pointing arrow indicates positive edge triggering, while a downward arrow shows negative edge triggering.

• CMOS flip-flops are active high, while many TTL flip-flops are active low.

The behaviour of the flip-flop is shown: When we send a pulse down the SET or RESET lines, the results can be shown in the truth table:

 S R Q Q-bar 0 0 1/0 0/1 0 1 0 1 1 0 1 0 1 1 1 1

The circuit shows how the D-type flip-flop can be made using NAND gates: What is meant by a circuit being transparent?

Counters

Latches can act as a memory for binary numbers that have been put into them.  Eight flip-flops can act as a memory for an eight-bit word, or a single byte.  In computers, which work with bytes, each eight-bit number stands for something, be it a letter, a number, or a character, determined by the ASCII code, universal for all computers.

Counters are special memories that store a word that represents the number of pulses that have passed into the circuit.  The D-type flip-flop is the simplest counter for 1 bit. The timing diagram shows the behaviour of the circuit: What do you notice about the output compared to the input?

This circuit can count two bits: When the reset is made high, the outputs Q go to give a two bit word BA 00.  The circuit then changes state on the falling edge of the clock pulse, according to the following table:

 Pulse B A 0 0 0 1 0 1 2 1 0 3 1 1 4 0 0

The word BA tells us the number of pulses that have arrived.  B is the most significant bit worth 21 (= 2), while A is the least significant bit worth 20 (= 1).  So BA = 11  represents 2 x 1 + 1 x 1 = 3. The timing diagram is like this: What do you notice about the output trace B?

Divide by 2 Circuit As well as acting as a single bit counter, the circuit above, which is a D-type flip-flop with feedback, acts as a divide by two circuit.  If we look at the timing diagram, we can see that the number of output pulses is half the number of clock pulses. When does the output trace change state?

The circuit works like this:

• The output Q-bar is 1 when Q is 0.

• On the first rising edge, Q changes to 1.

• And stays there as the clock pulse falls to 0.

• Then on the next clock pulse, the rising edge causes the output to change to 0.

• The output changes every other clock pulse.

4-bit Counters

We can cascade flip-flops so that we can have as many bits as we want.  The next diagram shows a four bit counter: This circuit is rising edge triggered, and each flip-flop has its Q-bar output fed back to the data input.  The timing diagram shows the idea: Notice that the unit counter goes through a change every two clock pulses, and the twos counter every four pulses.  The fours would be every eight pulses, and the eights every sixteen pulses.  If we look at the output of the counter, we would see it increase by 1 every two clock pulses.  This is an up-counter.

 What is the maximum decimal number that this counter can count to?

To make a down-counter, we connect the Q-bar output to the CK input of the next flip-flop, while the Q output is connected to the data input. 4-bit Ring Counter

A 4-bit ring counter is a serial input parallel output shift register (SIPO)  that has the output of the last counter which has a line connecting the final output with the input (Click HERE for more about shift registers.  They are NOT on the syllabus.) It works like this:

1. All the flip-flops are set to 0 by sending a pulse along the reset line.

2. The input is set to 1 before the clock is set going. This makes Q3 to be 1.  Q0 is 1 as well because it's directly connected to the input.

3. On the next clock pulse the 1 in Q3 is passed to Q2.  The 0 in Q1 is passed to Q0.  So the input becomes 0.

4. Then the 1 is passed from Q2 to Q1.  Q0 is 0 and the input is 0.  Q3 and Q2 are 0 as well.

5. Finally the 1 gets passed to Q0 and is fed back to the input.

We can sum this up in this table:

 Clock Q3 Q2 Q1 Q0 Start 1 0 0 1 1 0 1 0 0 2 0 0 1 0 3 0 0 0 1 4 1 0 0 0

So the 1 gets cycled around.  The idea is shown in the diagram: This is often called a modulo-4 counter as it has 4 states before it repeats itself.  If you wanted 8 states, you would have 8 flip-flops to make a modulo-8 counter.  Similarly you would need 16 flip-flops to make a modulo-16 counter.  This can be rather inefficient.

Johnson Counter

This is a very similar counter, except that the feedback is taken from the Q-bar output.  Alternatively you can put a NOT-gate into the feedback, as has been done here: The inversion causes the counting to be done in a different way, shown in the table below:

 Clock Q3 Q2 Q1 Q0 Start 0 0 0 0 1 1 0 0 0 2 1 1 0 0 3 1 1 1 0 4 1 1 1 1 5 0 1 1 1 6 0 0 1 1 7 0 0 0 1 8 0 0 0 0

While the normal 4-bit counter can circulate 4 different combinations, the Johnson counter can circulate 8 different combinations.  Its modulus is twice the number of the flip-flops.  The Johnson counter is often called a Modulo-2n counter.

A 3-stage Johnson counter can be used as a 3-phase square wave generator, with each phase being 120o apart.

A 5-stage Johnson counter can be used as a decade counter.

Modulo N Counters

The 4-bit counters we have seen above count from 0 to 15 (decimal) before resetting to zero.  We say that it is a modulo 16 counter.  The modulo refers to the number of states that a counter goes through until it resets to zero.

A counter with n flip-flops will go through 2n states before it resets to zero.

If we want to reset to zero before that 2nth state is reached, we need to add an AND gate to the circuit and feed the output of the AND gate to the reset line.  The diagram shows the four bit counter with the AND gate feeding the reset line: The counter counts up to binary 1010 (decimal 10).  Since Q1 and Q3 are 1, the output of the AND gate is 1 and that makes the reset line 1, knocking the counter back to zero.  This circuit is called a binary coded decimal (BCD) counter.  We could chose any of the lines.  The AND gate between Q2 and Q3 would give us a modulo 12 counter. Why is the circuit above a Modulo-12 counter?